1. Field of the Invention
This invention relates to a semiconductor chip and the methods for fabricating the same. More particularly, this invention relates to a semiconductor chip fabricated by a simplified process.
2. Description of the Related Art
Due to the advancement that the information technology industry has made in recent decades, fast access to information far away is no longer impractical. To reach an advantageous position of business competition, various electronic products have been installed in components. With the evolution of the information industry, the latest generation of IC chips has, overall, much more abundance on functions than before. Attributed to the improvements in the semi-conductor technology, the improvements in the production capability of the innovative IC chips becomes a continual trend in the past few decades.
Also affiliated with the development of copper interconnection technology, today's IC design becomes ever sophisticated, with a far more number of transistors being placed in a single IC chip through each generations of development. Putting more circuitry in a scaled down IC chip has another important merit other than adding multiple functions to the chip. That is, the length of data paths among the transistors also becomes shorter, which is beneficial to distributing signals readily.
In order to package the highly integrated IC chip, metal traces and bumps can be formed over the passivation layer of the IC chip in a bumping fab after the chip is manufactured by a conventional IC fab. The procedure and steps of forming the metal traces and bumps over the IC passivation layer are described as below.
FIGS. 1-12 are schematic cross-sectional illustrations of the conventional process which forms the circuits/metal traces and bumps on a semiconductor wafer. Referring now to FIG. 1, a semiconductor wafer 100 comprising a semiconductor substrate 110 multiple thin-film dielectric layers 122, 124 and 126, multiple thin-film circuit layers 132, 134 and 136 and a passivation layer 140 is shown.
Multiple electronic devices 112 are deposited in or on the semiconductor substrate 110. The semiconductor substrate 110, for example, is a silicon substrate. The electronic devices 112 is formed in or on the semiconductor substrate 110 through doping penta-valence ions (5A group in periodic table), such as phosphorus ions, or doping tri-valence ions (3A group in periodic table), such as boron ions. The electronic devices 112 formed by this process can be metal oxide semiconductor (MOS) devices, or transistors.
Multiple thin-film dielectric layers 122, 124, and 126, made of materials such as silicon oxide, silicon nitride, or silicon oxynitride, are deposited over the active surface 114 of semiconductor substrate 110. The multiple thin-film circuit layers 132, 134, and 136 are deposited respectively on the multiple thin-film dielectric layers 122, 124, and 126, with the multiple thin-film circuit layers 132, 134, and 136 being composed of materials such as aluminum, copper or silicon. A plurality of via holes 121, 123, and 125 are respectively in the multiple thin-film dielectric layers 122, 124, and 126. The multiple thin-film circuit layers 132, 134, and 136 are connected to each other or to the electronic devices 112 through via holes 121, 123, and 125.
A passivation layer 140 is formed over the multiple thin-film dielectric layers 122, 124, and 126 and over the multiple thin-film circuit layers 132, 134, and 136. The passivation layer 140 is composed of either silicon nitride, silicon oxide, phosphosilicate glass, or a composite having at least one of the above listed materials. Multiple openings 142 in the passivation layer 140 expose the uppermost thin-film circuit layer 136.
In FIGS. 2-6, a schematic cross-sectional view of the conventional method for forming circuit/metal traces on the passivation layer of a semiconductor wafer is shown. Referring now to FIG. 2, a sputtering process is used to form an bottom metal layer 152 over passivation layer 140 of the semiconductor wafer 100 and on the multiple thin-film circuit layer 136, which is exposed through the opening 142 in the passivation layer 142. Next, a photoresist layer 160 is formed over the bottom metal layer 152, as shown in FIG. 3. An opening 162 in the photoresist layer 160 exposes the bottom metal layer 152. Subsequently, an electroplating method is used to form the patterned circuit layer 154 on the bottom metal layer 152 exposed by the opening 162 in the photoresist layer 160, as illustrated in FIG. 4. Then, the photoresist layer 160 is removed, as demonstrated in FIG. 5. Afterwards, as shown in FIG. 6, the bottom metal layer 152 not covered by the patterned circuit layer 154 is etched away by a wet etching process, using the patterned circuit layer 154 as the etching mask. So far a patterned metal trace 150 combining the bottom metal layer 152 and the patterned circuit layer 154 is created.
Referring now to FIG. 7, a polymer layer 170 is formed over the circuit/metal trace 150 and over the passivation layer 140, with an opening 172 in the polymer layer 170 exposing the circuit/metal trace 150.
In FIGS. 8-12, a schematic cross-sectional view of the conventional process for forming a bump over a passivation layer of a semiconductor wafer is shown. Referring now to FIG. 8, a sputtering method is used to form an adhesion/barrier layer 182 over the polymer layer 170 and on the circuit/metal trace 150 exposed by the opening 172 in the polymer layer 170. Next, a photoresist layer 190 is formed on the adhesion/barrier layer 182, as shown in FIG. 9. An opening 192 in the photoresist layer 190 exposes the adhesion/barrier layer 182. Then, an electroplating method is used to form the patterned metal layer 184 on the adhesion/barrier layer 182 exposed by the opening 192 in the photoresist layer 190, as shown in FIG. 10. Subsequently, as illustrated in FIG. 11, the photoresist layer 190 is removed. Then, as shown in FIG. 12, the uncovered section of the adhesion/barrier layer 182 is etched away, with the patterned metal layer 184 serving as an etching mask. So far, the bump 180 combining the adhesion/barrier layer 182 and the patterned metal layer 184 can be created.
Referring now to FIGS. 1-12, both of the procedures for creating the circuit/metal trace 150 and the bump 180 comprise a sputtering process to create the bottom metal layers 152 and 182 and an etching technique to remove the uncovered portion of bottom metal layer 152 and 182 after forming the patterned metal layers 154 and 184. Thereby, the conventional process for forming the circuit/metal trace 150 and the bump 180 is inefficient in that it performs two etching processes and two sputtering processes to achieve the goal.